This application is based upon and claims priority from prior French Patent Application No. 0010814, filed on Aug. 22, 2000, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The invention relates to electrostatic discharge protection of integrated circuits, and more particularly the protection of an nMOS transistor incorporated in an output cell of an integrated circuit.
2. Description of the Prior Art
At the present time, electrostatic discharge protection of an integrated circuit is provided by placing, for example, specific protection devices in the supply cells or else locally in parallel with the output cell of the integrated circuit.
Such protection devices protect the integrated circuits by providing a low-resistance path during an electrostatic discharge.
However, such protection devices have certain drawbacks. One of them relates to the robustness of the protection device itself. Another drawback relates to the triggering of undesirable conduction within a particularly sensitive component of the integrated circuit, for example an nMOS output transistor placed in parallel with the protection device.
The reason for this is that, in advanced CMOS technologies, nMOS transistors are sensitive and a low overvoltage at their terminals can be sufficient to initiate conduction within the parasitic bipolar transistor formed between the source and the drain of the nMOS transistor. This undesirable current flow between the source and the drain of the nMOS transistor may accelerate the appearance of defects in the nMOS transistor.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
The invention aims to remedy these drawbacks as discussed above.
It is an object of the invention to provide an electrostatic discharge protection device that prevents any undesirable MOS conduction through the output transistor during an electrostatic discharge and which consequently delays the triggering of the parasitic bipolar transistor and the appearance of defects.
A preferred embodiment of the present invention therefore provides an electrostatic discharge protection device for an integrated transistor called an xe2x80x9coutputxe2x80x9d transistor. According to a general aspect of the invention, this device comprises a switching transistor, connected between the gate of the output transistor and ground, and control means connected to the gate of the switching transistor. The control means is capable of ensuring that the switching transistor is off when there is no electrostatic discharge at the drain of the output transistor and capable of turning the switching transistor on when there is an electrostatic discharge at the drain of the output transistor.
In other words, when an electrostatic discharge occurs at a package pin connected to the drain of the output transistor, the device according to the invention ensures that the potential of the output transistor gate is pulled down to ground. Thus, any undesirable conduction within the transistor is avoided. In contrast, during normal operation of the integrated circuit, the protection device is transparent with respect to the integrated circuit. In other words, the device has no influence on the gate of the output transistor.
According to one embodiment of the device according to the invention, the control means comprises:
a capacitor (for example formed by a pMOS transistor whose drain and source are connected together), a first terminal of which is connected to the gate of the switching transistor and the second terminal of which is electrically coupled to the drain of the output transistor (that is to say to the contact that it is desired to protect) during the electrostatic discharge;
a first supply terminal electrically dissociated from the drain of the transistor during the electrostatic discharge; and
a first transistor (for example, an nMOS transistor), the gate of which is connected to the first supply terminal, the source of which is connected to ground and the drain of which is connected to the gate of the switching transistor.
Thus, during normal operation of the integrated circuit, the first transistor is on, thereby putting the gate of the switching transistor at ground potential. The latter is consequently off. The protection device therefore has no influence on the gate of the output transistor.
When the integrated circuit is not in operation, that is to say not supplied, it is consequently not biased and capacitively coupled to ground. Consequently, the first supply terminal is not biased and has a low potential. During an electrostatic discharge at the drain of the output transistor, the potential at this drain rises. The potential at the second terminal of the capacitor, which is electrically connected to the drain of the output transistor during this electrostatic discharge, also rises.
Since the first supply terminal is electrically dissociated from the drain of the transistor during the electrostatic discharge, the potential at this supply terminal does not rise, thereby allowing the first terminal to remain in the off state. This can therefore be likened to a capacitor (formed between the drain and the source of this transistor). Because of the capacitive bridge formed by the capacitor, the first transistor in its off state, and the switching transistor, a rise in voltage occurs on the gate of the switching transistor, thereby turning it on and consequently connecting the gate of the output transistor to ground and consequently turning the latter off.
Of course, a person of ordinary skill in the art will know how to adjust the ratio of the capacitance of the capacitor to the sum of the capacitances of the first transistor and of the switching transistor so as to obtain, during an electrostatic discharge, a voltage at the gate of the switching transistor such that the gate-source voltage of this switching transistor is greater than the threshold voltage of this switching transistor.
However, it will be advantageous to choose a capacitive ratio such that the capacitance of the capacitor formed, for example, by the pMOS transistor is greater than the sum of the capacitances of the first transistor and of the switching transistor, so as to further increase the effectiveness of the turning on of the switching transistor during an electrostatic discharge.
According to a preferred embodiment of the invention, the control means comprises a second supply terminal dissociated from the first supply terminal and connected to the drain of the output transistor. The second terminal of the capacitor is therefore connected to the second supply terminal.
It is also possible according to another embodiment to replace the first transistor with a resistive element and/or to use a single supply.